The present invention relates generally to resistive memory apparatus, and more particularly to apparatus comprising one or more memory cell units containing a plurality of resistive memory elements in which a resistive memory material is used for information storage.
This section is intended to provide a background or context to the invention disclosed below. The description herein may include concepts that could be pursued, but are not necessarily ones that have been previously conceived, implemented or described. Therefore, unless otherwise explicitly indicated herein, what is described in this section is not prior art to the description in this application and is not admitted to be prior art by inclusion in this section.
Resistive memory cells such as phase-change memory (PCM) cells use a resistive memory material for storage of information. The resistance of such cells can be programmed via a programming (or “write”) operation that changes the relative proportions of high- and low-resistance regions of the resistive memory material of the cell. The resulting cell-resistance can be measured in a subsequent “read” operation to determine the programmed cell-state. In a PCM cell, for example, the relative proportions of a (high-resistance) amorphous phase and a (low-resistance) crystalline phase of a chalcogenide material disposed between terminals of the cell can be varied by application of control signals to the cell terminals. The relative proportions of the amorphous and crystalline regions of the cell material resulting from programming can be controlled via the applied signals.
In single-level memory devices, cells can be set to one of two states, a high-resistance “RESET” state and a low-resistance “SET” state, permitting storage of one bit per cell. Multilevel devices exploit additional, intermediate states, corresponding to differing proportions of the high- and low-resistance regions within the cell volume. In PCM cells, for example, the RESET state corresponds to a substantially amorphous state of the PCM material. The SET state corresponds to a substantially crystalline PCM material. The additional programming states for multilevel operation correspond to different sizes of the amorphous region within the otherwise-crystalline cell volume. Since the two material phases exhibit a large resistance contrast, varying the size of the amorphous region within the overall cell volume produces a corresponding variation in cell-resistance. The cell-resistance, and hence programmed cell-state, can be read at any time by applying a low-voltage signal to the cell terminals and measuring the resulting “read current” flowing through the cell. The signal level for the read operation is sufficiently low that the read operation does not disturb the programmed cell-state.
There are currently efforts to develop 3D (three-dimensional) resistive memory architectures in which two-dimensional arrays of resistive memory cells are layered one above the other to produce an integrated 3D memory structure. An example of such a memory structure is described in U.S. Pat. No. 8,169,819 B2. Such memory architectures offer the potential for significantly higher storage capacity and areal efficiency. Most of the 3D efforts are still at the development stage and are based on a BEOL (back end of line) process to define the memory architecture in which individual cells can be written/read. It is widely believed that such BEOL-compatible 3D efforts cannot lead to a significant number of memory layers (e.g. >5 layers) due to challenges associated with microfabrication as well as difficulties associated with addressing individual devices. Moreover, for reliable operation, prior devices are restricted to storing 1-bit per cell because resistive memory cells are subject to resistance variations such as resistance drift over time drift, substantial flicker noise, and resistance that varies with ambient temperature. These effects, which are largely attributable to the high-resistance regions of the resistive memory material of cells, cause resistance measurements for different cell-states to vary with time in a stochastic manner. Such effects inhibit reliable readback for multilevel operation where the resistance levels of different cell-states are more closely packed, and therefore harder to distinguish in the presence of stochastic resistance variations. These problems present a significant challenge in the drive to increase storage densities and areal efficiency of resistive memory devices.
Improvements in resistive memory devices would be highly desirable.